1. Field of the Invention
The present invention relates to the field of generating a periodic signal-, more particularly, the present invention relates to a method and apparatus for generating a periodic signal using a delay locked loop.
2. Description of Related Art
Phase-locked loops (PLLs), synchronous delay lines (SDLs), and delay locked loops (DLLs) are used to generate an output clock signal that locks onto the period of an input clock signal.
These circuits use a charge pump that drives an analog control voltage to be received by sample and hold (S/H) circuits. The sampled analog control voltage is used to control a voltage-controlled oscillator (VCO) in a PLL and a voltage-controlled delay line in an SDL or DLL. Noise and mismatching between capacitors of the S/H circuits causes instability in the output clock signal (clock jitter). Clock jitter reduces the maximum frequency of operation of a device and may lead to device malfunction. In addition, charge pumps use large capacitors. The cost of a silicon device is related to the silicon area. Thus, these circuits may be relatively expensive to produce.
Lock time is the number of clock cycles required for the output clock signal to lock onto the period of the input clock signal. Since the device operation does not reliably begin until after a stable output clock is generated, the lock time is a component of the latency for the device to operate after power-up. SDLs, PLLs, and DLLs have lock times on the order of thousands of clock cycles. Thus, there is; a delay of thousands of clock cycles before the device begins to operate after power up. High latency leads to reduced performance. Furthermore, test procedures for a device during a manufacturing process typically include many power-up sequences. Thus, the latency increases the time to test the device and therefore increases manufacturing costs.
Similarly, if the period of the input clock signal is changed, there may be a latency of thousands of clocks for the output clock signal to lock onto the new period of the input clock signal. Thus, there is a delay of thousands of clock cycles before the device begins to operate after an operating frequency change. An operating frequency change may be performed, for example, to conserve power when the device is idle.
Furthermore, the use of analog circuitry in a digital device, such as a microprocessor, typically tends to make manufacturing more complex. Optimal manufacturing process conditions for analog circuitry is often different than that of digital circuitry. Compromises are often required. Thus, it is desirable to manufacture a purely digital device to permit the use of a manufacturing process that is optimized for digital circuitry without the additional complexity and, in some cases, reduced performance and/or yield due to the use of analog circuitry.
What is needed is a method and apparatus to reduce clock jitter in a device used to lock an output clock signal onto the period of an input clock signal. What is needed is a method and apparatus to reduce cost in a device used to lock an output clock signal onto the period of an input clock signal. What is needed is a method and apparatus to reduce the lock time in a device used to lock an output clock signal onto the period of an input clock signal. What is needed is a purely digital device to lock an output clock signal onto the period of an input clock signal.